The present disclosure relates generally to the field of semiconductor devices and, more particularly, to techniques for increasing uniformity of wear in semiconductor devices.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present techniques, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Electrical systems often include components that use one or more semiconductor devices (e.g., semiconductor elements), such as diodes and transistors. For example, the electrical system may be a computing system that uses semiconductor devices in logic circuits of microcomputers, memory, and gate arrays for digital logic functionality. The electrical system, or a portion of the electrical system, may occasionally operate in low-power modes to improve operational efficiency, such as power consumption. In low-power modes however, the semiconductor devices in the logic circuits may receive static (e.g., idle) data signals for long periods of time. The consistent stress on the semiconductor devices, which occurs when the semiconductor devices remain in the same state for extended periods of time due to the static data signals, may increase susceptibility of the devices to reliability issues. For example, the steady-signal wear may cause additional wear due to negative-bias temperature instability (NBTI) as compared to when the devices operate in default modes.
The increased susceptibility may lead to degradation of device performance. For example, switching speed of the devices may slow down due to degradation by NBTI. Further, the deterioration of device performance due to NBTI may vary between devices and circuit paths of the logic circuits, resulting in non-uniform wear of the devices and timing violations by the logic circuits. Accordingly, embodiments of the present disclosure may be directed to techniques for controlling uneven wearing on devices due to NBTI.